1. Field of the Invention
The present invention generally relates to the design and manufacture of integrated circuits and printed-circuit electronic packages whose structures consist of several layers of conducting, insulating and other materials that are structured in the horizontal dimension by fabrication processes and, more particularly, to a method of computing a maximum space restriction between shapes and generating shape complements without denesting the hierarchical data structure that defines the shapes, thereby considerably reducing the output data and the consequent processing time.
2. Background Description
Semiconductor integrated circuits and printed circuit electronic packages are generally structures consisting of several layers of conducting, insulating and other materials that are structured in the horizontal dimension by fabrication processes that transfer patterns defined in physical designs or layouts. These physical designs or layouts are typically represented as computer data consisting of two dimensional shapes in a hierarchical data structure that exploit the repetitive structure usually found in such circuits and packages. Some physical rule checking or shapes processing involves the distance or area between shapes. In particular, some integrated circuit chip processes impose a "maximum space" restriction between shapes on some fabrication layers. While minimum space methods are well established, the maximum space computation is difficult.
In some cases, the action of the fabrication processes is affected by the design patterns being transferred to the physical materials. For example, the local pattern density of the design, i.e., the fraction of area over which material is deposited (or removed) can affect the shapes and dimensions of features, with the "locality extent" dependent on the specific fabrication process. As a specific example, this can occur in reactive ion etching (RIE), in which an excess in local pattern density (meaning that less material is to be etched away) causes nearby pattern features to be too small (i.e., "overetched") due to relatively high concentration of etchants. This effect appears to act at a length scale of hundreds of micrometers to millimeters. Other processes that may be affected by local pattern density include lithographic patterning of resist materials and chemical-mechanical (so called "chemech") polishing (CMP).
The standard process for verifying maximum spacing of structures in the design has been to work on the design in flattened, or denested, form. An efficient representation for rule checking or shapes processing is to determine the complement of the designed shapes, which is then used for subsequent processing. The standard process for creating the complement of a design level is again to flatten, or denest, the shapes and subtract (complement) them from a frame. The problems with those methods which denest the hierarchical design data are as follows:
Every instance of every shape must be handled, which consumes computer processing time. PA1 The result of the operation, a complemented design level, contains too much data to process efficiently.
Thus, what is needed is a maximum space computation method which processes the design data without denesting and an efficient generation of shape complementation, again without denesting the design data.